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Thread: Anandtech News

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    #8801

    Anandtech: AMD Next Horizon Live Blog: Starts 9am PT / 5pm UTC

    AMD's 2019 is set to be full of 7nm products, and on the back of AMD's New Horizon event on 2016, today it is hosting part two: Next Horizon. In CEO Dr. Lisa Su's welcome letter, it states that AMD is set to 'enter a new chapter in [its] journey to deliver the datacenter of the future'. I'm here in San Francisco to get all the details on what appears to be discussions and presentations about the next generation EPYC and 7nm Vega, as well as customer responses and deployments about AMD's current datacenter portfolio.
    Come back to this page at 9am Pacific Time when then event is set to start, and come follow our live blog.

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    Anandtech: Intel Architecture Event Announced: December 11th

    On the back of a series of recent announcements regarding Intel’s future product line and portfolio, Intel has disclosed to us that it will be holding a forward-looking Architecture Summit/Event in a few weeks. The event will be an exclusively small affair, with only a few press invited, but an opportunity for Intel to discuss its future vision for the next few months with engineers and technical fellows set to give some detailed presentations.
    One of the most frequent requests we have put to Intel over the recent months is for a return to an Intel that offers more information. In previous years, Intel would dive deep into its product portfolio and its architecture designs in order to showcase its engineering talent and prowess. This often happened at the awesome annual Intel Developer Forum, a yearly event held in the heart of San Francisco, but since it was disbanded a couple of years ago, the level of detail in each subsequent launch has been agonizingly minimal. For an engineering company that used to proudly present its technical genius on a stage, in detail, to suddenly become so very insular about its R&D raised a lot of questions. It would appear our persistence is paying off, and Intel is going to do something about it.
    Details on the content of the Intel Architecture Summit/Event are slim at this point, as invites are slowly being handed out. At this point we are not immediately aware whether Intel intends to have an embargo. In the past at these sort of events, some of the information became almost immediately available, while some of the meatier details had longer embargo times to allow for the press to get to grips with the information and ask questions and write articles. When Intel discussed the Skylake design in detail before it hit the shelves, there was a short lead time. This event is likely to be along the same lines.
    At this point we do not know exactly what Intel will be discussing – the only thing we’ve been told is that it will be ‘update’ with Intel’s architects and technical fellows focusing on architecture. This could extend into CPU, GPU, AI, and everything in-between, and if we’re lucky, manufacturing. Given that Cascade Lake is a known part at this point, it would be difficult to see Intel discussing more on the CPU side unless they have an ace in the design we don’t already know about. A far more interesting topic would be on the GPU side, assuming that Raja Koduri and his team have something to say. We already know that the Nervana Neural Network Processor is due out in 2019, so there could be some detail to discuss there as well. An outside possibility is Intel talking 10nm. One can hope.
    I’ll be attending for AnandTech. I hope this ends up being a good event, so that there are more like it in the future.
    Buy Intel Core i9-9900K on Amazon.com


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    #8803

    Anandtech: AMD Unveils ‘Chiplet’ Design Approach: 7nm Zen 2 Cores Meet 14 nm I/O Die

    AMD on Tuesday disclosed some additional details about its upcoming codenamed Rome processor based on its Zen 2 microarchitecture. As it turns out, the company will use a new design approach with its next-generation EPYC CPUs that will involve CPU ‘chiplets’ made using TSMC’s 7 nm manufacturing technology as well as an I/O die made using a 14 nm fabrication process.
    AMD’s chiplet design approach is an evolution of the company’s modular design it introduced with the original EPYC processors featuring its Zen microarchitecture. While the currently available processors use up to four Zen CPU modules, the upcoming EPYC chips will include multiple Zen 2 CPU modules (which AMD now calls ‘chiplets’) as well as an I/O die made using a mature 14 nm process technology. The I/O die will feature Infinity Fabrics to connect chiplets as well as eight DDR DRAM interfaces. Since the memory controller will now be located inside the I/O die, all CPU chiplets will have a more equal memory access latency than today’s CPU modules. Meanwhile, AMD does not list PCIe inside the I/O die, so each CPU chiplet will have its own PCIe lanes.
    Separating CPU chiplets from the I/O die has its advantages because it enables AMD to make the CPU chiplets smaller as physical interfaces (such as DRAM and Infinity Fabric) do not scale that well with shrinks of process technology. Therefore, instead of making CPU chiplets bigger and more expensive to manufacture, AMD decided to incorporate DRAM and some other I/O into a separate chip. Besides lower costs, the added benefit that AMD is going to enjoy with its 7 nm chiplets is ability to easier bin new chips for needed clocks and power, which is something that is hard to estimate in case of servers.
    This is a breaking news. We are updating the news story with more details.
    Source: AMD


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    #8804

    Anandtech: AMD Announces Zen 4 Microarchitecture Under Development

    At its Next Horizon event in San Francisco, AMD announced the fourth iteration of its Zen microarchitecture. The Zen 4 is currently in development, so the company does not share many details about it right now.
    Right now, the company is sampling its codenamed Rome CPUs based on Zen 2 microarchitecture and made using TSMC’s first-generation 7 nm manufacturing technology (N7). After that, AMD plans to release a processor based on its Zen 3 architecture and these chips will be made using TSMC’s N7+ fabrication process that will take advantage of EUV lithography. Since Zen 4 microarchitecture is still in design phase, chances are that processors on its base will be made using a more advanced node, so think 5 nm, but keep in mind that any guesses today are speculations at best.
    At its event AMD implied that the first CPUs based on its Zen 3 microarchitecture will ship in 2020, so it is natural to expect Zen 4 to reach actual products in 2021 or later. As for what to expect from the new microarchitecture, the company naturally promised higher performance and performance per watt when compared to prior generations.
    Previously AMD has only discussed Zen 2 and Zen 3 microarchitectures, yet it is not surprising that the company will keep evolving its successful design in the coming years.
    This is a breaking news. We are updating the news story with more details.
    Related Reading:


    Source: AMD



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    #8805

    Anandtech: AMD Previews EPYC ‘Rome’ Processor: Up to 64 Zen 2 Cores

    AMD on Tuesday formally announced its next-generation EPYC processor code-named Rome. The new server CPU will feature up to 64 cores featuring the Zen 2 microarchitecture, thus providing at least two times higher performance per socket than existing EPYC chips.
    As discussed in a separate story covering AMD’s new ‘chiplet’ design approach, AMD EPYC ‘Rome’ processor will carry multiple CPU chiplets manufactured using TSMC’s 7 nm fabrication process as well as an I/O die produced at a 14 nm node. As it appears, high-performance ‘Rome’ processors will use eight CPU chiplets offering 64 x86 cores in total.
    Gallery: AMD EPYC 'Rome' CPU: A Hands On


    This is a breaking news. We are updating the news story with more details.


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    Anandtech: AMD Announces Radeon Instinct MI60 & MI50 Accelerators: Powered By 7nm Veg

    As part of this morning’s Next Horizon event, AMD formally announced the first two accelerator cards based on the company’s previously revealed 7nm Vega GPU. Dubbed the Radeon Instinct MI60 and Radeon Instinct MI50, the two cards are aimed squarely at the enterprise accelerator market, with AMD looking to significantly improve their performance competitiveness in everything from HPC to machine learning.
    Both cards are based on AMD’s 7nm GPU, which although we’ve known about at a high level for some time now, we’re only finally getting some more details on. GPU is based on a refined version of AMD’s existing Vega architecture, essentially adding compute-focused features to the chip that are necessary for the accelerator market. Interestingly, in terms of functional blocks here, 7nm Vega is actually rather close to the existing 14nm “Vega 10” GPU: both feature 64 CUs and HBM2. The difference comes down to these extra accelerator features, and the die size itself.
    With respect to accelerator features, 7nm Vega and the resulting MI60 & MI50 cards differentiates itself from the previous Vega 10-powered MI25 in a few key areas. 7nm Vega brings support for half-rate double precision – up from 1/16th rate – and AMD is supporting new low precision data types as well. These INT8 and INT4 instructions are especially useful for machine learning inferencing, where high precision isn’t necessary, with AMD able to get up to 4x the perf of an FP16/INT16 data type when using the smallest INT4 data type. However it’s not clear from AMD’s presentation how flexible these new data types are – and with what instructions they can be used – which will be important for understanding the full capabilities of the new GPU. All told, AMD is claiming a peak throughput of 7.4 TFLOPS FP64, 14.7 TFLOPS FP32, and 118 TOPS for INT4.
    7nm Vega also buffs up AMD’s memory capabilities. The GPU adds another pair of HBM2 memory controllers, giving it 4 in total. Combined with a modest increase in memory clockspeeds to 2Gbps, and AMD now has a full 1TB/sec of memory bandwidth in the GPU’s fastest configuration. This is even more than NVIDIA’s flagship GV100 GPU, giving AMD the edge in bandwidth. Meanwhile as this is an enterprise-focused GPU, it offers end-to-end ECC, marking the first AMD GPU to offer complete ECC support in several years.
    The enterprise flourishes also apply to 7nm Vega’s I/O options. On the PCIe front, AMD has revealed that the GPU supports the recently finalized PCIe 4 standard, which doubles the amount of memory bandwidth per x16 slot to 31.5GB/sec. However AMD isn’t stopping there. The new GPU also includes a pair of off-chip Infinity Fabric links, allowing for the Radeon Instinct cards to be directly connected to each other via the coherent links. I’m still waiting for a confirmed breakdown on the numbers, but it looks like each link supports 50GB/sec down and 50GB/sec up in bandwidth.
    Notably, since there are only 2 links per GPU, AMD’s topology options will be limited to variations on rings. So GPUs in 4-way configurations won’t all be able to directly address each other. Meanwhile AMD is still sticking with PCIe cards as their base form factor here – no custom mezzanine-style cards like NVIDIA – so the cards are connected via a bridge on the top. Meanwhile backhaul to the CPU (AMD suggests an Epyc, of course) is handled over PCIe 4.
    Finally, looking at the GPU itself, it’s interesting to note just how small it is. Because AMD didn’t significantly bulk up the GPU on CUs, thanks to the 7nm process the new GPU is actually a good bit smaller than the original 484mm2 Vega 10 GPU. The new GPU comes in at 331mm2, packing in 13.2B transistors. Though it should be noted that AMD’s performance estimates are realistically conservative here; while 7nm does bring power consumption down, AMD is still only touting >1.25x performance of MI25 at the same power consumption. The true power in the new cards lies in their new features, rather than standard FP16/FP32 calculations that the existing MI25 card was already geared for.
    Wrapping things up, Radeon Instinct MI60 will be shipping in Q4 of this year. AMD has not announced a price, but as a cutting-edge 7nm GPU, don’t expect it to be cheap. MI60 will then be followed by MI50 in Q1 of next year, giving AMD’s customers a second, cheaper option to access 7nm Vega.
    Gallery: Rome Presentation Slide Deck




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    #8807

    Anandtech: ChipRebel Releases Kirin 980 Die Shot: Cortex A76's & Mali G76 in View

    When new flagship silicon chips are released, one thing that I always eagerly await is somebody publishing a die shot of said design. Over the past few years this has always been done by ChipWorks and subsequently TechInsights – but last year a little known site called ChipRebel caught my attention when they released a very high quality, high-resolution shot of the Apple A11. I’ve been in touch with the folks over there over the past few weeks, poking to see what their plans were, and was happy to hear that they’re trying to gain more traction in the future.
    Yesterday ChipRebel released a preliminary teardown of the new Huawei Mate 20 – and along with it publicly released a low-res version of their Kirin 980 die shot, along with their commercial high-resolution shot. This is very exciting, as the new HiSilicon chip marks the second commercially available consumer 7nm chip – of course after Apple’s own A12 from just a few weeks prior. More importantly, this is the first time we’re seeing Arm’s new Cortex A76 CPUs as well as the new Mali G76 GPU.
    I took the liberty to label some of the some more obvious block complexes of the SoC image on my own, and also shared this with the folks over at ChipRebel:

    Die shot credit: ChipRebel - Block labelling: AnandTech
    Second commercial 7nm SoC - Another tiny die!

    First of all – the Kirin 980 is quite a lot smaller than HiSilicon had led to people to believe: Back when the chipset was announced, they had mentioned it was “under 100mm²”, with many thinking the die would be somewhere in the ballpark just below that figure. In reality, the Kirin 980 measures just a mere 74.13mm² - a 30% reduction compared to last year’s 96.72mm² Kirin 970 – even though the new chipset brings a lot of new features and more complexity.
    On the top left corner we can see the new Mali G76MP10 GPU. The Mali G76 drastically differs from past generation Arm GPUs in that it essentially doubles the computational capabilities of each core – in effect that one could say that the new MP10 core configuration in the Kirin 980 is about equivalent to a MP20 of the previous generation – microarchitectural improvements aside.
    On the right side we see the new CPU complex. This is HiSilicon’s first DynamIQ CPU configuration, as the company’s release schedule for the Kirin 970 last year made them miss out on the Cortex A75. For the Kirin 980 however, we see a configuration that fully takes advantage of the new DynamIQ flexibility: We have essentially one large CPU cluster, with different CPUs attached to it.
    The centre complex is the DSU, the DynamIQ Shared Unit, essentially the L3 cache controller along with the tag RAMs as well as the large 4MB L3 cache itself. Flanked on both sides of the DSU we see the 4 Cortex A55 cores that clock up to 1.8GHz, each of these also sport private 128KB L2 caches.
    Really nice to see on the die shot is the two pairs of Cortex A76 cores. HiSilicon employs the four cores into pairs, with each pair running on a dedicated voltage and frequency plane. We can see that the physical implementation between the two pairs very evidently differs, and this would confirm my suspicion that we’re looking at a frequency optimised pair, running at up to 2.6GHz, and a more power optimised pair, limited to 1.92GHz. Both pairs employ 512KB private L2 caches on each core.
    An interesting thing is that it’s again extremely difficult to even locate the NPU on even the Kirin 980. HiSilicon describes this as a dual-core unit, however I can’t seem to find any matching block on the shot – if the company is using non-identical layouts for the two “cores”, then all bets are off in trying to identify this easily.
    Overall, it’s great to have a new player in the die shot imaging scene, and hopefully the folks over at ChipRebel are able to gain more attention in order to be able to continue to share with us images of important future chip developments.
    I’m finishing up my review of the Mate 20 and Mate 20 Pro – and we’ll go into more detail into the performance and power of the new Kirin 980 and the new Cortex A76 CPUs as well as the new Mali G76, so stay tuned!


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    #8808

    Anandtech: The Be Quiet! Straight Power 11 750W PSU Review: Excellent Quality, But No

    In today's review we are taking a look at the latest Straight Power 11 series from Be Quiet!, a German manufacturer. The Straight Power 11 units are not the highest tier that the company currently offers, yet the company still rates them (and appraises them) as a premium series, boasting that they can deliver excellent overall performance, reliability, and, above all else, near-silent operation.

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    Anandtech: Netgear Announces Nighthawk RAX80 and RAX120 802.11ax AX6000 Routers

    Netgear has announced imminent availability of their first 802.11ax router - the 8-stream Nighthawk RAX80, along with the technical details, pricing, and other information. In addition, they have also unveiled the 12-stream RAX120. While the RAX80 will be available for purchase this month, RAX120 will make it to retail in Q1 2019.
    802.11ax has had an uphill adoption curve. Silicon vendors have been announcing draft-compliant chipsets since late 2016 (Quantenna - Q4 2016, Qualcomm - Q1 2017, Broadcom - Q3 2017, Marvell - Q4 2017, and Intel - Q1 2018). Device vendors were not far behind, with Asus going public about its plans to release a router (RT-AX88U) based on the Broadcom platform as early as September 2017. A year after the announcement, the RT-AX88U finally made it to retail at a $350 price point. D-Link also gave a sneak peek into their AX6000 and AX11000 routers based on the Broadcom chipset at the 2018 CES. In the meanwhile, we have had deployments of the Qualcomm chipset in the carrier gateways from KDDI and NEC in Asia, as well as enterprise access points from Huawei and Ruckus Wireless.
    Netgear had hinted at their 802.11ax product stack in their 2018 Analyst Day presentation. Today's launch provides concrete details of their first-generation 802.11ax products.
    The benefits of 802.11ax have been brought out in multiple articles before, but, a recap of the major improvements is in order:

    • Availability of both uplink and downlink OFDMA (orthogonal frequency-division multiple access) to improve spectral efficiency
    • Usage of both 2.4 GHz and 5 GHz bands (unlike the 5 GHz-only 802.11ac standard)
    • Standardization of 1024-QAM and and making MU-MIMO a mandatory feature (dissimilar to its optional downlink-only nature in 802.11ac Wave-2)

    It must be noted that the aim of 802.11ax is not to target peak data-rates, but, improve the aggregate performance over several simultaneously active clients. The OFDMA-enabled simultaneous transmission to several users results in increased efficiency. Thanks to the lowered waiting time, the battery life of client devices also increases.
    The first 802.11ax product to ship from Netgear will be the Nighthawk RAX80 AX6000 router based on the Broadcom BCM49408 SoC with two 802.11ax radios - the BCM43684. The BCM49408 has a 1.8 GHz quad-core ARMv8 processor (Cortex A53) supplemented by a 800 MHz network packet co-processor that keeps the main CPU free for other tasks. The radios are in a 4x4:4 configuration, with one dedicated to 2.4 GHz duties (bgn+ax, with 40 MHz channels for 1150 Mbps of theoretical throughput), and another dedicated to the 5 GHz channel (an+ac+ax, with 160 MHz channel support for 4800 Mbps of theoretical throughput). The 8-stream configuration puts the Nighthawk RAX80 in the AX6000 class.
    Early next year, Netgear will be shipping the Nighthawk RAX120 AX6000 router based on the Qualcomm IPQ8078 SoC. This SoC appears to be a slightly tweaked version of the IPQ 8074 announced in Feburary 2017. The key difference is that the quad-core Cortex A53 cluster runs at 2.2 GHz (compared to the 2 GHz IPQ 8074 configuration). This SoC is complemented by two 802.11ax radios - the QCN5154 (an+ac+ax) and the QCN5124 (bgn+ax) for the 5 GHz and 2.4 GHz channels. The radios are in a 8x8:8 and 4x4:4 configuration respectively. The router will still be in the AX6000 class, just like the RAX80 - because the 8x8:8 configuration doesn't support 160 MHz channels (only 80 MHz). The IPQ8078 SoC comes with an integrated NBASE-T MAC, which is used by the RAX120 to enable a 5 Gbps LAN port. The PHY duty for this port is handled by the Aquantia AQR108.
    There are a few aspects that differentiate the RAX80 and the RAX120:

    • The RAX80's spatial streams configuration is 4x4:4 + 4x4:4 in the 2.4 GHz and 5 GHz bands, while the RAX120's configuration is 4x4:4 + 8x8:8
    • The RAX80 can support 160 MHz-wide channels and DFS, and those features are enabled in the launch firmare, while the RAX120 will initially ship with 80 MHz channels and no DFS.
    • The RAX120 platform can support DFS, and that is in the firmware roadmap. The Qualcomm platform used in the RAX120 can also support 160 MHz channels, but, the spatial stream configuration drops down to 4x4:4 in that case. Netgear indicated that 4x4:4 160 MHz channel support for the RAX120 is also in the firmware roadmap.
    • The RAX120 will be the first WPA3-certified consumer router from Netgear. WPA3 certification for the RAX80 is also planned, but, it will not be done in time for its retail launch.
    • The RAX80 claims multi-gig support using link-aggregation, while the RAX120 comes with a N-BASET LAN port (up to 5 Gbps). The NBASE-T port is currently set for LAN duties, but the firmware roadmap indicates that it could potentially be used as a WAN port in the future.
    • The RAX80 supports both uplink and downlink OFDMA, but, the RAX120 supports only downlink OFDMA.

    The RAX80 and RAX120 differentiate themselves from the other 802.11ax routers announced so far by opting for a very different industrial design. Instead of going with the traditional antennae, the routers comes with a couple of 'wings' in which the antennae are hidden. With pre-positioning for optimal performance, and wall-mount capability for the unit, Netgear claims that the routers can fit practically anywhere to deliver high-end Wi-Fi performance.
    The RAX80 comes with 5x GbE LAN ports and 1x GbE WAN port, along with a couple of USB 3.0 ports.The RAX80 allows for link-aggregation across its LAN ports, and also between the WAN and one of the LAN ports. The latter allows for full compatibility with upcoming multi-gigabit Internet uplinks, though Netgear currently does not have any modems with dual LAN ports supporting link aggregation.
    Netgear RAX80 Link Aggregation
    The RAX120 comes with (4x 1Gbps + 1x 5Gbps) LAN and a 1Gbps WAN port. Just like the RAX80, the router also sports a couple of USB 3.0 ports. Link aggregation is supported on two of the 1Gbps LAN ports. Netgear is marketing the NBASE-T connection as a flexible multi-gig port.
    Netgear RAX120 NBASE-T Support
    The absence of 802.11ax clients has definitely held back the adoption of 802.11ax a bit. However, Netgear was quick to stress that the new routers would enable even advanced 802.11ac clients with Wave 2 features to benefit. The RAX80 supports 160 MHz-wide channels and is also DFS (dynamic frequency selection) certified out of the box. Thanks to the non-availability of a contiguous 160 MHz wide-channel in the permitted operation spectrum, DFS support is absolutely essential if the full advantage of such wide channels is to be realized.
    Even though both routers are in the AX6000 class, the availability of more spatial streams in the RAX120 is helpful when we have a large number of clients that are simultaneously active. On the other hand, DFS and 160 MHz channels support out of the box should help provide better peak rates for single clients capable of supporting that configuration. NBASE-T support in the AX12 gives it a slight edge compared to the link-aggregation routine that is not straightforward for the average consumer. However, the firmware status for the AX12 seems fairly fluid, and its launch is also a few months away. For the 2018 holiday season, it appears that Netgear is putting its bets on the AX8 as its flagship router.
    The Nighthawk RAX80 is priced at $400, and is available for pre-order now (with shipping date set to late December 2018). Netgear did not provide any pricing information for the RAX120 that will make it to retail in Q1 2019.


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    #8810

    Anandtech: AMD EPYC for ATX Workstations: GIGABYTE MZ01-CE0 & MZ01-CE1 Motherboards

    AMD’s EPYC processor has made it into servers and supercomputers, yet it still has to find its place inside workstations. To a large degree that is because up until recently there were no motherboards for these CPUs on the market. ASRock Rack was first to showcase such a mainboard at Computex. Now, GIGABYTE is coming up not with one, but with two ATX mobos for AMD’s EPYC aimed at workstations.
    GIGABYTE’s lineup of ATX motherboards for AMD’s EPYC consists of two motherboards, the MZ01-CE0 and MZ01-CE1. Both feature a socket for AMD’s EPYC, four PCIe x16 slots (as expected from a CPU that has 64 spare PCIe lanes) compatible with dual-slot graphics cards and accelerators, a PCIe x8 slot, eight DDR4 slots supporting up to 1 TB of DDR4 ECC memory, an M.2 slot for SSDs, and four SlimSAS ports for up to 16 SATA storage devices.
    Despite being ATX-compatible, the two motherboards from GIGABYTE can be used to build both workstations as well as servers. The MZ01-CE0 and MZ01-CE1 platforms come equipped with Aspeed’s AST2500 BMC for remote management as well as GIGABYTE’s Server Management software.
    Both MZ01-CE0 and MZ01-CE1 motherboards come equipped with two onboard Intel I210 GbE LAN controllers. Meanwhile, the MZ01-CE0 is also outfitted with two extra 10 GbE Base-T LAN ports (controlled by the Intel X550 chip) for those who have appropriate networks for transferring large files from one system to another (something quite common in movie industry, for example).
    GIGABYTE has not touched upon MSRPs of its EPYC-supporting motherboards because they will be available mostly to B2B customers. Meanwhile, being unique products for server CPUs and equipped with expensive network controllers, the MZ01-CE0 and MZ01-CE1 will certainly carry premium price tags.
    GIGABYTE's ATX Motherboards for AMD EPYC CPUs
    MZ01-CE0 MZ01-CE1
    Supported CPUs AMD Socket 4094
    AMD EPYC processors with up to 32 cores and 180 W TDP
    PCH AMD
    Graphics Aspeed’s AST2500 BMC
    4 × PCIe 3.0 x16 slot
    Display Outputs 1 × D-Sub
    Memory 8 × DDR4 DIMM
    Up to 1 TB of DDR4 with ECC
    Slots for Add-In-Cards 4 × PCIe 3.0 x16
    1 × PCIe 3.0 x8
    Ethernet LAN 1: Intel I210AT GbE PHY
    LAN 2: Intel I210AT GbE PHY
    LAN 3: Intel X550 10 GbE PHY
    LAN 4: Intel X550 10 GbE PHY
    MLAN: Realtek RTL8211E
    LAN 1: Intel I210AT GbE PHY
    LAN 2: Intel I210AT GbE PHY
    MLAN: Realtek RTL8211E
    Storage M.2 1 × M.2-22110 (PCIe 3.0 x4)
    SATA 16 × SATA 6 Gbps via four SlimSAS ports
    Audio none
    USB 2 × USB 3.1 Gen 1 Type-A
    Serial Ports 2 × internal COM port
    Other I/O 1 × TPM header (some SKUs come with pre-installed TPM)
    2 × internal USB Type-A (for front panel)
    Monitoring CPU Temperature
    Fan RPM
    Management GIGABYTE Server Management (GSM)
    Aspeed AST2500 management controller
    Avocent MergePoint IPMI 2.0 web interface
    Compatibility Windows Server 2012 R2 (x64)
    Windows Server 2016
    Red Hat Enterprise Linux 6.9
    Red Hat Enterprise Linux 7.3
    SUSE Linux Enterprise Server 11.4
    SUSE Linux Enterprise Server 12 .2
    Ubuntu 16.04
    Ubuntu 17.04
    VMware ESXi 6.5
    Form-Factor ATX (305 mm × 244 mm | 12" × 9.6")
    Related Reading:


    Source: GIGABYTE


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